1. Field of the Invention
The present invention relates to an apparatus and a method for a serial peripheral interface, and more particularly, to a slave and a master of a serial peripheral interface, a system thereof, and a method thereof, in which the transmission of the read address is can be saved.
2. Description of the Related Art
The parallel peripheral interface of the address and data bus is commonly used as an access interface for the flash memory. However, such interface uses a great number of pins, which is costly in packaging chips. In order to reduce the number of pins in the chip, several methods have been applied. Among them, the serial peripheral interface (abbreviated as SPI hereinafter) is commonly adopted in the industry.
FIG. 1 schematically shows a waveform diagram illustrating the timing of performing a read operation on a conventional SPI. The SPI structure complied with the standard specification uses a serial clock signal line (SCK) and a serial transmission data line (DQ) to transmit data. Referring to the waveform in FIG. 1, wherein SCK is a serial clock signal on the serial clock signal line, DQ is a line signal on the serial transmission data line, and CS_B is an enable signal. The SPI standard defines a specific transmission protocol, in which a master of SPI is triggered on every positive edge of the clock based on the serial clock signal SCK in order to transmit command and address on the serial transmission data line (DQ). Similarly, a slave of SPI is triggered on every negative edge of the clock based on the serial clock signal SCK to send back the data on the serial transmission data line (DQ).
FIG. 2 schematically shows a waveform diagram illustrating the timing of performing a fast read operation on a conventional SPI. Wherein, the command and the address on the serial transmission data line (DQ) are still transmitted on the positive edge trigger of the serial clock signal SCK. However, since the frequency of the serial clock signal SCK is too high in such case, when the slave of SPI sends back the data, one or more dummy data cycles are added in order to accurately read data and to ensure data can be accurately and promptly read.
In the prior art, each read process on the SPI comprises: transmitting a command, transmitting an address, and receiving a data. Since the command and address need to be retransmitted every time when the data is read, such design reduces the efficiency of the data read. Especially when performing the fast read command, since the frequency of the transmission clock is too high, one or more dummy data cycles have to be added between the address and data that the data can be accurately and promptly read, which increases transmission time and reduces the transmission efficiency.